This invention relates to charged-particle-beam lithography and, more particularly, to a technique for scanning such a beam over the surface of a workpiece in a precise high-speed manner.
Considerable interest exists in utilizing an electron beam exposure system for selectively irradiating a resist-coated workpiece to define therein microminiature features of a large-scale-integrated (LSI) circuit. By controlling the beam in a highly accurate and high-speed way, it is possible to make masks for LSI circuits or to pattern a resist-coated semiconductor wafer to define the features of such circuits directly without employing masks.
An advantageous electron beam exposure system (EBES) for LSI lithography is described in U.S. Pat. No. 3,900,737, issued to R. J. Collier and D. R. Herriott. The system described therein is a practical tool for generating high-quality fine-featured LSI masks and is also capable of exposing patterns directly on resist-coated semiconductor wafers.
The EBES exposure process requires a beam of emitted electrons to be focused to a submicron size on an electron-sensitive resist layer. In practice, the diameter of the spot is also the address dimension of the system. In one particular embodiment of EBES, the focused electron spot is scanned in raster fashion across a subregion of the layer.
Various modification of EBES are possible to adapt it to meet the ever increasing demand for devices with very small feature sizes. Thus, for example, if it is desired to write 0.5-micrometer (.mu.m)-minimum-linewidth features with 0.125-.mu.m resolution, using the EBES scanning mode, an electron spot 0.125-.mu.m in diameter can be employed. With high-brightness electron sources and sensitive resists, such small-spot EBES systems have the potential to serve as advantageous tools for fabricating LSI devices. But, in practice, to achieve acceptable pattern-writing speeds with such a small-spot system, it is necessary that the spot be scanned over the resist layer in a very-high-speed way. In one such specific illustrative system, the per-address exposure time during linear scanning is only approximately one nanosecond. This obviously imposes severe and difficult requirements on certain portions of the electrical circuitry included in the EBES system for precisely controlling movement of the electron spot over the resist layer.
Linear scanning of a small electron spot at very high rates in an EBES system is feasible. But, as the scanning rate is increased, the ability of the electrical circuitry in the system to precisely and reproducibly control the turning on and turning off of the spot at the beginning and end of a scan line has, heretofore, reached a point at which the end points of the scan line are no longer exactly defined with consistency. In turn, this means that at very high scanning rates the edges of features being patterned with the scanning spot are no longer defined precisely. For certain high-resolution applications, the scanning rate and therefore the throughput of EBES systems are accordingly limited by the ability of the circuitry therein to turn the scanning spot on and off with high precision.
Efforts have been directed at trying to reliably increase the turn-on and turn-off speeds of a scanning electron spot in an EBES system. Such efforts have been directed, for example, at trying to design improved high-speed circuitry for accomplishing the turn-on and turn-off functions. It was recognized that such efforts or some equivalent thereof, if successful, could significantly increase the throughput characteristics of a high-resolution EBES system.